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AS5510
Datasheet - Detailed Description
The communication from the AS5510 includes:
n Reading the magnetic field strength in 10-bit data
n Reading the status bits
Note: The I?/SPAN>C address of the chip is selected by hardware (pin ADR). Depending on the state of this pin, the I?/SPAN>C address is either
Pin ADR = LOW ? I睠 address = 1010110b(56h)
Pin ADR = HIGH ? I睠 address = 1010111b(57h)
7.2.1 I睠 Interface Data
Note: Operating conditions T
amb
= -30 to +85癈, VDD=2.5 to 3.6V (3V operation) unless otherwise noted.
Table 7. I睠 Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
f
SCLK
SCL clock frequency
1
MHz
t
BUF
Bus free time; time between STOP and
START condition
0.5
約
t
HD.STA
Hold time; (repeated) START
condition
1
1. After this time the first clock is generated
0.26
約
t
LOW
LOW period of SCL clock
0.5
約
t
HIGH
HIGH period of SCL clock
0.26
約
t
SU.STA
Setup time for a repeated START
condition
0.26
約
t
HD.DAT
Data hold time
2
2. A device must internally provide a hold time of at least 120ns (Fast-mode Plus) for the SDA signal (referred to the V
IHmin
of the SCL) to
bridge the undefined region of the falling edge of SCL.
0.45
約
t
SU.DAT
Data setup time
3
3. A fast-mode device can be used in standard-mode system, but the requirement t
SU.DAT
= 250ns must then be met. This is automatically
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL sig-
nal, it must output the next data bit to the SDA line t
Rmax
+ T
SU.DAT
= 1000 + 250 = 1250ns before the SCL line is released.
50
ns
t
R
Rise time of SDA and SCL signals
120
ns
t
F
Fall time of SDA and SCL signals
4
4. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be consid-
ered for bus timing.
120
ns
t
SU.STO
Setup time for STOP condition
0.26
約
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